Low voltage NMOS-based electrostatic discharge lamp

ABSTRACT

Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the field of semiconductors. Moreparticularly, the invention relates to a low voltage electrostaticdischarge clamp.

2. Discussion of the Related Art

Electrostatic discharge (ESD) is an important reliability concern formost classes of integrated circuits. In order to protect the circuitcore, a circuit designer may use a protective element connected inparallel with the circuit, connecting an input/output (I/O) pad to theground. However, providing an ESD protection element that is able toshunt high levels of ESD current while maintaining low clampingvoltages, that uses a relatively small area, and that is compatible withexciting IC process technologies is particularly challenging.

An ESD protection element must provide a high level of protection withminimum parasitic loading area. Additionally, an ESD protection deviceis required to exhibit a failure current that is large and that properlyscales with the area of the protection device itself.

An unsatisfactory approach to protecting a circuit from ESD includesutilizing a floating-body n-channel metal-oxide semiconductor (NMOS)device. Floating-body NMOS transistors may be used as ESD clamps andusually present good ESD protection. Nevertheless, problems with thistechnology include a high direct leakage current (DC leakage) andgreater susceptibility to latch-up. In the case of an NMOS transistor,for example, DC leakage may be in the form of an undesirable currentfrom the drain to the source. Latch-up may occur, for example, when theparasitic thyristor structures formed by the NMOS and adjacent devicesare inadvertently triggered.

Thus, there is need for a device which presents good ESD protectioncharacteristics with low DC leakage and high latch-up immunity.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings accompanying and forming part of this specification areincluded to depict certain aspects of the invention. A clearerconception of the invention, and of the components and operation ofsystems provided with the invention, will become more readily apparentby referring to the exemplary, and therefore nonlimiting, embodimentsillustrated in the drawings, wherein like reference numerals (if theyoccur in more than one view) designate the same or similar elements. Theinvention may be better understood by reference to one or more of thesedrawings in combination with the description presented herein. It shouldbe noted that the features illustrated in the drawings are notnecessarily drawn to scale.

FIG. 1 is a combination circuit and block diagram of a prior-art ESDprotection system.

FIG. 2 is a combination circuit and block diagram of an ESD protectionsystem, representing an embodiment of the invention.

FIG. 3 is a combination circuit and block diagram of another ESDprotection system, representing an embodiment of the invention.

FIG. 4 is a cross-section of an isolated RPWT NMOS transistor,representing an embodiment of the invention.

FIG. 5 is a graph of a transmission line pulse (TLP) curve 402characteristic of an RPWT clamp such as the one detailed in FIG. 2 or 3and of a TLP curve 401 characteristic of a prior-art clamp such as theone detailed in FIG. 1, illustrating one aspect of the invention.

FIG. 6 is a graph of a direct leakage current (DC leakage) curve 501characteristic of an RPWT clamp such as the one detailed in FIG. 2 or 3and of a DC leakage curve 502 characteristic of a prior-art clamp suchas the one detailed in FIG. 1, illustrating one aspect of the invention.

DETAILED DESCRIPTION

The invention and the various features and advantageous details thereofare explained more fully with reference to the nonlimiting embodimentsthat are illustrated in the accompanying drawings and detailed in thefollowing description. Descriptions of well known starting materials,processing techniques, components and equipment are omitted so as not tounnecessarily obscure the invention in detail. It should be understood,however, that the detailed description and the specific examples, whileindicating specific embodiments of the invention, are given by way ofillustration only and not by way of limitation. Various substitutions,modifications, additions and/or rearrangements within the spirit and/orscope of the underlying inventive concept will become apparent to one ofordinary skill in the art from this disclosure.

According to an aspect of the invention, a method includes protecting acircuit from an electrostatic discharge by coupling a resistor p-wellconnected transistor to an input/output pad and to a ground in parallelwith the circuit.

According to another aspect of the invention, a resistor p-wellconnected transistor includes a substrate, an isolating structure in thesubstrate, an isolating layer adjacent to the isolating structure, awell adjacent to the isolating layer and the isolating structure, afirst doped region in the well, a first conducting terminal adjacent tothe first doped region defining a body, a second doped region in thewell, a second conducting terminal adjacent to the second doped regiondefining a source, a dielectric layer adjacent to the well, a thirdconducting terminal adjacent to the dielectric layer defining a gate, athird doped region in the well, a fourth conducting terminal adjacent tothe third doped region defining a drain, and a resistive element coupledbetween the first conducting terminal and the second conductingterminal.

Referring to FIG. 1, a combination circuit and block diagram of aprior-art ESD protection system 100 is depicted. A floating-bodytransistor (or clamp) 101, having a body 102, a gate 103, a source 104,and a drain 105 is connected to an I/O pad 110 via the drain 105, and toa ground 120 via the source 104. The gate 103 is connected to the source104. A circuit or circuit core 130 is connected to the drain 105 and tothe source 104, in parallel with the floating-body transistor 101.

The floating-body transistor 101 may be an n-channel metal-oxidesemiconductor (NMOS) transistor, an isolated NMOS transistor, or thelike. The body 102 is floating, that is, its terminal has an undefinedvoltage.

In operation, the floating-body transistor 101 may function as a clampdue to its parasitic lateral NPN characteristics. The floating-bodytransistor operates as bipolar junction transistor (BJT) in breakdownmode, which may typically handle large amounts of current with a low“on” resistance, thereby reducing the total power dissipation. Ideally,during an ESD event, the floating-body transistor 101 turns on(conducts) before the circuit 130 is damaged. The floating-bodytransistor 101 remains “off” (non-conducting) during normal circuitoperation.

Referring to FIG. 2, a combination circuit and block diagram of an ESDprotection system 200 is depicted according to an exemplary embodimentof the invention. An ESD protection transistor (or clamp) 201 having abody 202, a gate 203, a source 204, and a drain 205 is connected to theI/O pad 110 via the drain 205, and to a ground terminal 120 via thesource 204. The gate 203 is connected to the source 204. The body 202 iscoupled to the source 204 though a resistor 206. The circuit 130 isconnected to the drain 205 and to the source 204, in parallel with theESD protection transistor 201. In practice, the ESD protectiontransistor 201 may be “on-chip”, meaning that it is formed on the samesemiconductor substrate as circuit 130.

In one embodiment, the ESD clamp 201 may be a resistor p-well connectedtransistor 201, also referred to as a resistor p-well tied (RPWT)transistor 201. The RPWT transistor 201 may be a RPWT n-channelmetal-oxide semiconductor (NMOS) transistor, an RPWT isolated NMOStransistor, or the like.

In another embodiment, the ESD clamp 201 may be a resistor n-wellconnected transistor 201. The resistor n-well connected transistor 201may be a p-channel metal-oxide semiconductor (PMOS) transistor, anisolated PMOS transistor, of the like.

In operation, the RPWT transistor 201 can be viewed as an NPN junctiontransistor. When the parasitic lateral NPN process is “on”, the drain205 acts like a collector, the source 204 acts like an emitter, and thebody 202 acts like a base, thereby effectively protecting the circuit130. An ESD current passes through the RPWT transistor 201, flowing fromthe I/O pad 110 to the ground 120. The functioning of an NPN transistoris known to one of ordinary skill in the art. When the RPWT transistor201 is “off”, the resistor 206 may reduce a direct current leakage fromthe drain 205 to the source 204, and avoid latch-ups in RPWT transistor201.

The invention may include connecting a resistive element between thebody 202 and the source 204 of clamp 201. In one embodiment, resistor206 may be used as the resistive element. In another embodiment, atransistor or a switch may be used as the resistive element.

Referring to FIG. 3, a combination circuit and block diagram of anotherESD protection system 250 is depicted according to an exemplaryembodiment of the invention. Switch 207 may be, for example, an NMOStransistor. In this embodiment, a switch drain 208 is connected to thebody 202 of the ESD clamp 201, a switch source 209 is connected to thesource 204 of the ESD clamp 201, and a switch gate 210 is connected to avoltage supply V_(DD). In one embodiment, the voltage supply V_(DD) isthe same supply used by the circuit core 130.

In operation, when the voltage supply V_(DD) is on, the switch 207 has alow resistance (on-state). When the voltage supply V_(DD) is off, theswitch 207 has a high resistance (off-state). Thus, the switch 207effectively functions as a resistance when the power is off. As one ofordinary skill in the art will recognize in light of this disclosure,ESD events are more likely to occur when the power is off and thecircuit is handled by human contact.

Referring to FIG. 4, a cross-section of an isolated RPWT NMOS transistor(or clamp) 300 is depicted according to an exemplary embodiment of theinvention. A p-substrate 302 is adjacent to an n-well ring 303 and to an-doped layer 304. The n-well ring 303 and the n-doped layer 304 isolatea p-well 305 from the p-substrate 302. A p+ region 306, a first n+region 307, and a second n+ region 308 are adjacent to the p-well 305.

A first conducting terminal 309 is adjacent to the p+ region 306,defining the body 202. A second conducting terminal 311 is adjacent tothe first n+ region 307, forming the source 204. The first conductingterminal 309 is coupled to the second conducting terminal 311 through aresistor 317. A dielectric layer 313 is adjacent to the p-well 305 andto the first and second n+ regions 307, 308. The dielectric layer 313 isalso adjacent to a third conducting terminal 314, defining the gate 203.In one embodiment, the dielectric layer 313 may be a silicon dioxidelayer (SiO₂). The third conducting terminal 314 is adjacent to thesecond conducting terminal 311, directly coupling the gate 203 to thesource 204. A fourth conducting terminal 315 is adjacent to the secondn+ region 308, defining a drain 205.

In one embodiment, the n-well ring 303 may be substituted by anotherisolating structure such as, for example, a deep trench isolatingstructure. In another embodiment, the first, second, third and fourthconducting terminals 309, 311, 314, 315 may be metal terminals, or maybe made of any other conducting materials such as, for example,polysilicon.

The isolated RPWT NMOS transistor 300 may be used, for example, as theRPWT transistor 201 in the ESD protection system 200 depicted in FIG. 2.In one embodiment, the resistor 317 may be internal to the p-well 305.

When the isolated RPWT NMOS transistor 300 is “on”, an electronavalanche is created at a reverse biased drain junction, a drifting ofholes elevates the body potential, and the source diode is forwardbiased, thus making the source 204 act like an NPN emitter, the body 202act like an NPN base, and the drain 205 act like an NPN colletor. Whenthe RPWT NMOS transistor 300 is “off”, the resistor 317 may reduce a DCleakage from the drain 205 to the source 204 and avoid latch-up.

Referring to FIG. 5, a transmission line pulse (TLP) curve 402characteristic of an RPWT clamp such as the one detailed in FIG. 2 or 3is compared to a TLP curve 401 characteristic of a prior-art clamp suchas the one detailed in FIG. 1, illustrating one aspect of the invention.The vertical axis is the ESD current through an ESD protection device inmilliamperes. The horizontal axis is the voltage across the device involts.

Transmission line pulse testing is a well-known electrical analysis toolwhich mimics ESD events and may be used for ESD stress testing. A firstcross 403 indicates the failure point of the RPWT clamp, while a secondcross 404 indicates the failure point of the prior-art clamp. Curves401, 402 are substantially similar, showing that the RPWT clampdisclosed herein achieves an ESD performance similar to that of theprior-art, floating-body clamp.

Referring to FIG. 6, a direct current (DC) leakage curve 501 (opencircles) characteristic of an RPWT clamp such as the one detailed inFIG. 2 or 3 is compared to another DC leakage curve 502 (open squares)characteristic of a prior-art clamp such as the one detailed in FIG. 1,illustrating one aspect of the invention. The vertical axis is the DCleakage through an ESD protection device in amperes. The horizontal axisis the voltage across the device in volts.

Direct current leakage testing may be used to measure the currentleaking from the drain to the source of a transistor when a DC voltageis applied from the drain to the source of the transistor. As FIG. 6indicates, the DC leakage of the RPWT clamp 501 is significantly lessthan that of the prior-art, floating-body clamp 502, while maintainingequivalent ESD performance as shown in FIG. 5.

In another embodiment, the invention includes using another resistiveelement coupling the gate to the source of an RPWT transistor to producea gate-coupling effect and further improve ESD protection. The inventionmay include an RPWT NMOS transistor made of a low-voltage junctionisolated NMOS transistor with its body coupled to its source through aresistor. Further, the invention may include using the RPWT NMOStransistor to protect low-voltage MOS devices from ESD, while minimizingDC leakage and latch-ups.

The particular manufacturing process used for the RPWT transistor of thepresent invention is within the skill level of one of ordinary skill inthe art and is not essential as long as it provides the describedfunctionality. Normally those who make or use the invention may selectthe manufacturing process based upon tooling and energy requirements,the expected application requirements of the final product, and thedemands of the overall manufacturing process, as known in the art.

The terms “a” or “an”, as used herein, are defined as one or more thanone unless the specification explicitly states otherwise. The term“substantially”, as used herein, is defined as at least approaching agiven state (e.g., preferably within 10% of, more preferably within 1%of, and most preferably within 0.1% of). The term “another”, as usedherein, is defined as at least a second or more. The terms “including”and/or “having”, as used herein, are defined as comprising (i.e., openlanguage). The term “coupled”, as used herein, is defined as connected,although not necessarily directly, and not necessarily mechanically.

The appended claims are not to be interpreted as includingmeans-plus-function limitations. Subgeneric embodiments of the inventionare delineated by the appended independent claims and their equivalents.Specific embodiments of the invention are differentiated by the appendeddependent claims and their equivalents.

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 17. An electrostatic protection circuit for protecting acircuit having at least two terminals, including a first terminalcoupled to an input/output pad and a second terminal coupled to a groundterminal, the electrostatic protection circuit comprising a resistorp-well connected transistor having a resistive element, a body, a drain,a gate, and a source, wherein: the drain is coupled to the input/outputpad; the source is coupled to the ground terminal; the gate is coupledto the source; and the resistive element couples the body to the source.18. The electrostatic protection circuit of claim 17, the resistiveelement comprising a resistor.
 19. The electrostatic protection circuitof claim 17, the resistive element comprising a switch.
 20. Theelectrostatic protection circuit of claim 19, the resistive elementcomprising a transistor.
 21. The electrostatic protection circuit ofclaim 17, further comprising another resistive element coupling the gateto the source.
 22. The electrostatic protection circuit of claim 17, theresistor p-well connected transistor comprising a resistor p-wellconnected NMOS transistor.
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